module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
	localparam IDLE = 4'b0000;
    localparam S0 = 4'b1000;
	localparam S1 = 4'b0001;
	localparam S2 = 4'b0010;
	localparam S3 = 4'b0011;
	localparam S4 = 4'b0100;
	localparam S5 = 4'b0101;
	localparam S6 = 4'b0110;
	localparam S7 = 4'b0111;
	localparam S01 =4'b1001;
	
    reg [3:0]state;
    reg [3:0]next_state;
	
	always@(posedge clk)begin
		if(!resetn)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			IDLE:begin
                next_state=(resetn)?S01:IDLE;
			end
            S01:begin//delay,f=1
				next_state=S0;
			end
			S0:begin//*
				next_state=(x)?S2:S1;
			end
			S1:begin//0*
				next_state=(x)?S2:S1;
			end
			S2:begin//1*
				next_state=(x)?S2:S3;
			end
			S3:begin//10*
				next_state=(x)?S4:S1;
			end
			S4:begin//101,g=1
				next_state=(y)?S5:S6;
			end
			S5:begin//permanently g=1
				next_state=S5;
			end
			S6:begin
				next_state=(y)?S5:S7;
			end
			S7:begin//permanently g=0
				next_state=S7;
			end
		endcase
	end
    assign f=(state==S01)?1'b1:1'b0;
	assign g=(state==S4|state==S5|state==S6)?(1'b1):1'b0;
endmodule